The focus of the Imagine is to develop a programmable architecture that achieves
the performance of special purpose hardware on graphics and image/signal processing.
This is accomplished by exploiting stream-based computation at the application,
compiler, and architectural level. At the application level, we have cast several
complex media applications such as polygon rendering, stereo depth extraction,
and video encoding into streams and kernels. At the compiler-level, we have developed
programming languages for writing stream-based programs and have developed software
tools that optimize their execution on stream hardware. Finally, at the architectural
level, we have developed the Imagine stream processor, a novel architecture that
executes stream-based programs and is able to sustain over tens of GFLOPs over
a range of media applications with a power dissipation of less than 10 Watts.
The Imagine Stream Architecture is a novel architecture
that executes stream-based programs. It provides high performance with 48 floating-point
arithmetic units and a area- and power-efficient register organization. A streaming
memory system loads and stores streams from memory. A stream register file provides
a large amount of on-chip intermediate storage for streams. Eight VLIW arithmetic
clusters perform SIMD operations on streams during kernel execution. Kernel execution
is sequenced by a micro-controller. A network interface is used to support multi-Imagine
systems and I/O transfers. Finally, a stream controller manages the operation
of all of these units.
Stream Programming Model
for Imagine are programmed using the stream programming model. This model consists
of streams and kernels. Streams are sequences of similar data records. Kernels
are small programs which operate on a set of input streams and produce a set of
Imagine is programmed with
a set of languages and software tools that implement the stream programming model.
Applications are programmed in StreamC and KernelC. A stream scheduler maps StreamC
to stream instructions for Imagine and a kernel scheduler maps KernelC to VLIW
kernel instructions for Imagine. Imagine applications have been tested using a
cycle accurate simulator, named ISim, and are currently being tested on a prototype
Programmable Graphics and Real-time Media Applications
The Imagine stream processor combines full programmability with high performance.
This has enabled research into new real-time media applications such as programmable
A prototype Imagine processor
was design and fabricated in conjunction with Texas Instruments.and received by
Stanford on April 9, 2002. Imagine contains 21 million transistors and has a die
size of 16mm x 16mm in a 0.15 micron standard cell technology.
Processor Development Platform
A prototype development board was designed
and fabricated in conjunction with ISI-East Dynamic Systems Division. This board
has enabled experimental measurements of the prototype Imagine processor, experiments
on performance of multi-Imagine systems, and additional application and software
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