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The picoProcessor (pP) is an 8-bit processor. The picoProcessor has separate instruction and data memories. The instruction memory is 4K instructions in size, and data memory is 256 bytes.

The picoProcessor can also address I/O devices using up to 256 input ports and 256 output ports. Within the processor there are eight 8-bit general purpose registers r0 to r7. r0 is always read as zero and ignores writes.

There is also a return address stack of depth 4, an interrupt return register and Zero(Z) and Carry(C) condition codes. Pipeline architecture is employed. The instruction register fetches the next instruction from the instruction memory depending on the value in the program counter.

This is the ‘fetch’ cycle .The program counter is incremented using a program counter updating logic block. The instruction fetched by the instruction register is decoded by a decoding logic and the required control signals are generated and are registered.

This is the ‘decode’ cycle. Depending on the control signals generated, the corresponding execution units are enabled. The outputs are registered in the following clock cycle. This is the ‘execute’ cycle. The registered outputs are then writte to the register file or the memory in the ‘write back’ cycle.




Simulation: modelsim5.8c

Synthesis: Xilinx 9.1