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The AHB (Advanced High-performance Bus) is a high-performance bus in AMBA (Advanced Microcontroller Bus Architecture) family. This AHB can be used in high clock frequency system modules.

The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macro cell functions. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques.

AHB is a technology-independent and ensure that highly reusable peripheral and system macro cells can be migrated across a diverse range of IC processes and be appropriate for full-custom, standard cell and gate array technologies.

Generally, an AMBA-based microcontroller typically consists of a high-performance system backbone bus (AMBA AHB), able to sustain the external memory bandwidth, on which the CPU, on-chip memory and other Direct Memory Access (DMA) devices reside.

In this work, the design of the Advanced High-Performance Bus Protocol is developed which has the basic blocks such as Arbiter, Master, Slave and Decoder.

The arbitration mechanism is used to ensure that only one master has access to the bus at any one time and the AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. This AMBA-AHB protocol can be adopted in all the application provided the design should be an AHB compliant




Simulation: ModelSim XE III 6.4b.

Synthesis: XiLinx ISE 10.1.