The high growth of the semiconductor industry over the past two decades has put Very Large Scale Integration in demand all over the world. Digital Signal Processing has played a great role in expanding VLSI device area.
The recent rapid advancements in multimedia computing and high speed wired and wireless communications made DSP to grab increased attention.
For an N-point transformation the direct computation of the Discrete Fourier Transform (DFT) requires N 2 operations.
Cooley and Turkey explained the concept of Fast Fourier Transform (FFT) which reduces the order of computation to Nlog 2 N. Basically FFT decomposes the set of data to be transformed into a series of smaller data sets to be transformed. The size of FFT decomposition is called "radix". Then, it decomposes those smaller sets into even smaller sets.
In this work, the Radix-2 Butterfly Processor will be designed which includes the adder, subtractor and the twiddle factor multiplier. The complex multiplier algorithm will be used in order to achieve the efficient complex multiplication.
The Radix-2 Butterfly Processor will be modeled using VHDL language which is a Hardware Description Language (HDL) used to describe a digital system. The modeled design can be simulated using Modelsim tool and the intended functionality can be verified with the help of its simulation results and also it can be synthesized using the Xilinx tool
Synthesis: Xilinx 9.1