Sigma Delta PLL Modulator
proliferation of wireless products over past few years has been rapidly increasing.
New wireless standards such as GPRS and HSCSD have brought new challenges to wireless
transceiver design. One pivotal component of transceiver is frequency synthesizer.
major requirements in mobile applications are efficient utilization of frequency
spectrum by narrowing the channel spacing and fast switching for high data rates.
This can be achieved by using fractional- N PLL architecture. They are capable
of synthesizing frequencies at channel spacings less than reference frequency.
This will increase the reference frequency and also reduces the PLL's lock time.
N PLL has the disadvantage that it generates high tones at multiple of channel
spacing. Using digital sigma delta modulation techniques. we can randomize the
frequency division ratio so that quantization noise of the divider can be transferred
to high frequencies thereby eliminatory the spurs.
The advantages of this conventional
PLL modulator is that they offer small frequency resolution, wider tuning bandwidth
and fast switching speed. But they have insufficient bandwidth for current wireless
standards such as GSM. so that they cannot be used as a closed loop modulator
for digital enhanced codeless (DECT) standard. they efficiently filter out quantization
noise and reference feed through for sufficiently small loop bandwidth.
For wider loop band width applications
bandwidth is increased. but this will results in residual spurs to occur. this
due to the fact that the requirement of the quantization noise to be uniformly
distributed is violated. since we are using techniques for frequency synthesis
the I/P to the modulator is dc I/P which will results in producing tones even
when higher order modulators are used. with single bit O/P level of quantization
noise is less but with multi bit O/P s quantization noise increases.
the range of stability of modulator is reduced which will results in reduction
of tuning range. More over the hardware complexity of the modulator is higher
than Mash modulator. In this feed back feed forward modulator the loop band width
was limited to nearly three orders of magnitudes less than the reference frequency.
So if it is to be used as a closed loop modulator power dissipation will increase.
in order to widen the loop band width the close-in-phase noise must be kept within
tolerable levels and also the rise of the quantization noise must be limited to
meet high frequency offset phase noise requirements. At low frequencies or dc
the modulator transfer function has a zero which will results in addition of phase
noise. For that the zero is moved away from dc to a frequency equal to some multiple
of fractional division ratio. This will introduce a notch at that frequency which
will reduce the total quantization noise. Now the quantization noise of modified
modulator is 1.7 times and 4.25 times smaller than Mash modulator.
higher frequencies quantization noise cause distortion in the response. This is
because the step size of multi bit modulator is same as single bit modulator.
So more phase distortion will be occurring in multi bit PLLs. To reduce quantization
noise at high frequencies the step size is reduced by producing functional division
This is achieved by using a phase selection divider instead of control
logic in conventional modulator. This divider will produce phase shifts of VCO
signal and changes the division ratio by selecting different phases from the VCO.
This type of divider will produce quarter division ratios.
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