Fourth
generation wireless and mobile system are currently the focus of
research and development. Broadband wireless system based on orthogonal
frequency division multiplexing will allow packet based high data
rate communication suitable for video transmission and mobile internet
application. Considering this fact we proposed a data path architecture
using dedicated hardwire for the baseband processor. The most computationally
intensive part of such a high data rate system are the 64-point
inverse FFT in the transmit direction and the viterbi decoder in
the receiver direction. Accordingly an appropriate design methodology
for constructing them has to be chosen a) how much silicon area
is needed b) how easily the particular architecture can be made
flat for implementation in VLSI c) in actual implementation how
many wire crossings and how many long wires carrying signals to
remote parts of the design are necessary d) how small the power
consumption can be .This paper describes a novel 64-point FFT/IFFT
processor which has been developed as part of a large research project
to develop a single chip wireless modem.
ALGORITHM FORMULATION
The discrete
fourier transformation A(r) of a complex data sequence B(k) of length
N
where r, k ={0,1……, N-1} can be described as
Where WN = e-2?j/N . Let us consider that N=MT , ? = s+ Tt and k=l+Mm,where
s,l ? {0,1…..7} and m, t ? {0,1,….T-1}. Applying these
values in first equation and we get
This shows that it is possible to realize the FFT of length N by
first decomposing it to one M and one T-point FFT where N = MT,
and combinig them. But this results in in a two dimensional instead
of one dimensional structure of FFT. We can formulate 64-point by
considering M =T = 8
This shows that it is possible to express the 64-point FFT in terms
of a two dimensional structure of 8-point FFTs plus 64 complex inter-dimensional
constant multiplications. At first, appropriate data samples undergo
an 8-point FFT computation. However, the number of non-trivial multiplications
required for each set of 8-point FFT gets multiplied with 1. Eight
such computations are needed to generate a full set of 64 intermediate
data, which once again undergo a second 8-point FFT operation .
Like first 8-point FFT for second 8-point again such computions
are required. Proper reshuffling of the data coming out from the
second 8-point FFT generates the final output of the 64-point FFT
.
Fig. Signal flow graph of an 8-point DIT FFT.
For realization of 8-point FFT using the conventional DIT does not
need to use any multiplication operation.
The constants
to be multiplied for the first two columns of the 8-point FFT structure
are either 1 or j . In the third column, the multiplications of
the constants are actually addition/subtraction operation followed
multiplication of 1/?2 which can be easily realized by using only
a hardwired shift-and-add operation. Thus an 8-point FFT can be
carried out without using any true digital multiplier and thus provide
a way to realize a low- power 64-point FFT at reduced hardware cost.
Since a basic 8-point FFT does not need a true multiplier. On the
other hand, the number of non-trivial complex multiplications for
the conventional 64-point radix-2 DIT FFT is 66. Thus the present
approach results in a reduction of about 26% for complex multiplication
compared to that required in the conventional radix-2 64-point FFT.
This reduction of arithmetic complexity furthur enhances the scope
for realizing a low-power 64-point FFT processor. However, the arithmetic
complexity of the proposed scheme is almost the same to that of
radix-4 FFT algorithm since the radix-4 64-point FFT algorithm needs
52 non-trivial complex multiplications.