There is a saying in real estate; when land
get expensive, multi-storied buildings are the alternative solution. We have a
similar situation in the chip industry. For the past thirty years, chip designers
have considered whether building integrated circuits multiple layers might create
cheaper, more powerful chips.
Performance of deep-sub micrometer very
large scale integrated (VLSI) circuits is being increasingly dominated by the
interconnects due to increasing wire pitch and increasing die size. Additionally,
heterogeneous integration of different technologies on one single chip is becoming
increasingly desirable, for which planar (2-D) ICs may not be suitable.
The three dimensional (3-D) chip design strategy exploits the vertical dimension
to alleviate the interconnect related problems and to facilitate heterogeneous
integration of technologies to realize system on a chip (SoC) design. By simply
dividing a planar chip into separate blocks, each occupying a separate physical
level interconnected by short and vertical interlayer interconnects (VILICs),
significant improvement in performance and reduction in wire-limited chip area
can be achieved.In the 3-Ddesign architecture, an
entire chip is divided into a number of blocks, and each block is placed on a
separate layer of Si that are stacked on top of each other.
For 3-D ICs
The unprecedented growth of
the computer and the information technology industry is demanding Very Large Scale
Integrated ( VLSI ) circuits with increasing functionality and performance at
minimum cost and power dissipation. Continuous scaling of VLSI circuits is reducing
gate delays but rapidly increasing interconnect delays. A significant fraction
of the total power consumption can be due to the wiring network used for clock
distribution, which is usually realized using long global wires.
Furthermore, increasing drive for the integration of disparate signals (digital,
analog, RF) and technologies (SOI, SiGe, GaAs, and so on) is introducing various
SoC design concepts, for which existing planner (2-D) IC design may not be suitable.
integration to create multilayer Si ICs is a concept that can significantly improve
interconnect performance ,increase transistor packing density, and reduce chip
area and power dissipation. Additionally 3D ICs can be very effective large scale
on chip integration of different systems.
In 3D design architecture, and entire(2D) chips is divided into a number of blocks
is placed on separate layer of Si that are stacked on top of each other. Each
Si layer in the 3D structure can have multiple layer of interconnects(VILICs)
and common global interconnects.
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