Published on Feb 20, 2020
Engineering is a study of tradeoffs. In computer engineering the tradeoff has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design. This new tradeoff is between performance and power or energy consumption.
The computational requirements of early embedded systems were generally more modest, and so the performance-power tradeoff tended to be weighted towards power. "High performance" and "energy efficient" were generally opposing concepts.
However, new classes of embedded applications are emerging which not only have significant energy constraints, but also require considerable computational resources. Devices such as space rovers, cell phones, automotive control systems, and portable consumer electronics all require or can benefit from high-performance processors. The future generations of such devices should continue this trend.
Processors for these devices must be able to deliver high performance with low energy dissipation. Additionally, these devices evidence large fluctuations in their performance requirements. Often a device will have very low performance demands for the bulk of its operation, but will experience periodic or asynchronous "spikes" when high-performance is needed to meet a deadline or handle some interrupt event.
These devices not only require a fundamental improvement in the performance power tradeoff, but also necessitate a processor which can dynamically adjust its performance and power characteristics to provide the tradeoff which best fits the system requirements at that time.
Fast, Powerful but Cheap, and Lots of Control
These motivations point to three major objectives for a power conscious embedded processor. Such a processor must be capable of high performance, must consume low amounts of power, and must be able to adapt to changing performance and power requirements at runtime.
The objective of this seminar is to define a micro-architecture which can exhibit low power consumption without sacrificing high performance. This will require a fundamental shift to the power-performance curve presented by traditional microprocessors. Additionally, the processor design must be flexible and reconfigurable at run-time so that it may present a series of configurations corresponding to different tradeoffs between performance and power consumption.
These objectives and motivations were identified during the MORPH project, a part of the Power Aware Computing / Communication (PACC) initiative. In addition to exploring several mechanisms to fundamentally improve performance, the MORPH project brought forth the idea of "gear shifting" as an analogy for run-time reconfiguration. Realizing that real world applications vary their performance requirements dramatically over time, a major goal of the project was to design microarchitectures which could adjust to provide the minimal required performance at the lowest energy cost.
The MORPH project explored a number of microarchitectural techniques to achieve this goal, such as morphable cache hierarchies and exploiting bit-slice inactivity. One technique, multi-cluster architectures, is the direct predecessor of this work. In addition to microarchitectural changes, MORPH also conducted a survey of realistic embedded applications which may be power constrained. Also, design implications of a power aware runtime system were explored.
Trends in semiconductor technology suggest that the use of reconfigurable logic blocks within the processor will be desirable in the near future. IBM unveiled its eFuse chip-morphing technology, designed to enable processors to dynamically adjust themselves in response to problems or systems demands recently.
eFuse is a patented technology that combines software algorithms and microscopic electrical fuses that will produce chips that can adapt on the fly to increase performance or avoid problems. The technology can sense when the chip needs to increase performance or avoid a potential problem, and then can reconfigure the chip to meet the demands by tripping electrical fuses integrated into the chip. It can monitor and manage power consumption, repair problems and sense changes in demands on the chip. Chip makers can use the morphing technology to alter chips for systems makers depending on the needs of end-users.
Future uses could include autonomic processors that can self-monitor, self-heal and reconfigure themselves dynamically after they've been put into systems.
This paper has attempted to introduce the main concepts in the Morph project, an attempt to approach low power embedded system in a novel way - by attacking power consumption during those frequent times when less than peak performance is needed. The approach taken is that of adding an energy/performance “gear” - in such low performance demanding times, the intrinsic performance of the computer can be throttled back, and done so in ways where the energy per operation performed drops precipitously. The result should be a substantial improvement in the performance energy curve.
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