The project involves design of a simple RISC processor and simulating it. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the over all speed of the processor .
The RISC concept first originated in the early 1970's when an IBM research team proved that 20% of instruction did 80% of the work .The RISC architecture follows the philosophy that one instruction should be performed every cycle
In this work, we analyze MIPS instruction format, instruction data path, decoder module function and design theory based on RISC (Reduced Instruction Set Computer) CPU instruction set.
Furthermore, we design instruction fetch ( IF ) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module, address arithmetic module, check validity of instruction module, synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully.
The idea of this project was to create a RISC processor as a building block in VHDL than later easily can be included in a larger design. It will be useful in systems where a problem is easy to solve in software but hard to solve with control logic.
However at a high level of complexity it is easier to implement the function in software. In this project for simulation we use Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.