An Instruction Set Architecture (ISA) is the contract between software and hardware. Commercial ISAs (x86, Arm) require licences and royalties. RISC-V is an open, free ISA: anyone can design a compliant core without paying fees. Its modular design — a small mandatory base plus optional extensions — makes it ideal for tailoring minimal, efficient processors to IoT workloads.
Working principle
RISC-V starts from a tiny base integer set (RV32I). Designers add only the standard extensions they need — 'M' for multiply, 'A' for atomics, 'F/D' for floating point, 'C' for compressed 16-bit instructions to save memory. Crucially, the ISA reserves custom opcode space, so a chip can add domain-specific instructions (e.g. for AI or DSP) while staying compatible with the open toolchain.
| Property | Arm / proprietary | RISC-V |
|---|---|---|
| Licence | Royalty / fee | Free, open |
| Customisation | Restricted | Custom extensions allowed |
| Ecosystem | Mature | Rapidly growing |
| Modularity | Fixed profiles | Pick-and-choose extensions |
Why it mattersRemoving licence fees and enabling application-specific instructions lets startups and academics ship silicon affordably — a major reason RISC-V is surging in microcontrollers and AIoT chips.
Applications
- Low-power microcontrollers and wearables
- AIoT edge inference cores with custom ML extensions
- Secure elements and academic / research processors
References & further reading
- Waterman & Asanović (eds.), “The RISC-V Instruction Set Manual,” RISC-V International, 2019–2024.
- Asanović & Patterson, “Instruction Sets Should Be Free: The Case for RISC-V,” UC Berkeley TR, 2014.
- Gautschi et al., “Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT,” IEEE TVLSI, 2017.