Conventional processors separate memory and compute, so data shuttles back and forth across the von Neumann bottleneck, burning energy. Neuromorphic chips instead mimic the brain: many simple neuron-and-synapse cores integrate memory and processing locally and compute only when spikes occur, making them extraordinarily efficient for sparse data.
Working principle
Each core implements arrays of spiking neurons (often Leaky Integrate-and-Fire) whose synaptic weights are stored in adjacent memory. Communication uses Address-Event Representation (AER): when a neuron fires, only its address is routed on-chip — there is no global clock driving dense matrix multiplies. Some designs support on-chip learning via spike-timing-dependent plasticity. Emerging variants use memristor crossbars to perform analog in-memory multiply-accumulate.
| Property | CPU / GPU | Neuromorphic |
|---|---|---|
| Memory–compute | Separated | Co-located (in/near-memory) |
| Operation | Clocked, dense | Event-driven, sparse |
| Data type | Numeric arrays | Spikes / events |
| Strength | General compute | Low-power sensory inference |
| Examples | x86, NVIDIA GPU | Intel Loihi 2, IBM TrueNorth |
ScopeNeuromorphic hardware shines on always-on edge sensing where data is naturally sparse; it is not a general-purpose replacement for GPUs in dense training workloads.
Applications
- Ultra-low-power keyword spotting, anomaly detection and sensor fusion
- Event-camera vision for high-speed robotics and drones
- Brain–machine interfaces and adaptive prosthetics
References & further reading
- Davies et al., “Loihi: A Neuromorphic Manycore Processor with On-Chip Learning,” IEEE Micro, 2018.
- Merolla et al., “A million spiking-neuron integrated circuit (TrueNorth),” Science, 2014.
- Roy et al., “Towards spike-based machine intelligence with neuromorphic computing,” Nature, 2019.