Moore's-law scaling of single monolithic chips is slowing and increasingly expensive: huge dies have poor yield and mixing process nodes is wasteful. The chiplet approach disaggregates a system into smaller dies — each built on the optimal node — then re-integrates them in one package using advanced packaging and 3D stacking.
Working principle
Chiplets are connected with very short, dense links. 2.5D integration places dies side-by-side on a silicon interposer or bridge; 3D integration stacks dies vertically and connects them with through-silicon vias (TSVs) and hybrid bonding, drastically cutting interconnect length and energy. Open die-to-die standards such as UCIe let chiplets from different vendors interoperate.
| Property | Monolithic SoC | Chiplets |
|---|---|---|
| Yield | Falls with die size | High (small dies) |
| Process mixing | Single node | Best node per function |
| Reuse | Low | High (mix & match) |
| Interconnect | On-die | Die-to-die (UCIe, bridge) |
| Challenge | Cost at large size | Packaging, thermals |
Key challengeHeat removal and the die-to-die interface dominate chiplet design; 3D stacks concentrate power density, making thermal-aware floorplanning essential.
Applications
- High-performance CPUs/GPUs and AI accelerators (HBM-on-package)
- Cost-optimised SoCs mixing advanced and mature nodes
- Heterogeneous integration of compute, memory and photonics
References & further reading
- Naffziger et al., “Pioneering Chiplet Technology … AMD EPYC and Ryzen,” ISCA 2021.
- UCIe Consortium, “Universal Chiplet Interconnect Express Specification,” 2022–2024.
- Lau, “Recent Advances and Trends in Heterogeneous Integration Packaging,” IEEE Trans. CPMT, 2022.