Since the fabrication of MOSFET, the minimum channel length has been shrinking
continuously. The motivation behind this decrease has been an increasing interest
in high-speed devices and in very large-scale integrated circuits. The sustained
scaling of conventional bulk device requires innovations to circumvent the barriers
of fundamental physics constraining the conventional MOSFET device structure.
The limits most often cited are control of the density and location of dopants
providing high I on /I off ratio and finite sub threshold slope and quantum-mechanical
tunneling of carriers through thin gate from drain to source and from drain to
channel depletion width must scale with the channel length to contain the off-state
leakage I off. This leads to high doping concentration, which degrade the carrier
mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant
profile control, in terms of depth and steepness, becomes much more difficult.
The gate oxide thickness tox must also scale with the channel length to maintain
gate control, proper threshold voltage VT and performance. The thinning of the
gate dielectric results in gate tunneling leakage, degrading the circuit performance,
power and noise margin.
device structures based on silicon-on-insulator (SOI) technology have emerged
as an effective means of extending MOS scaling beyond bulk limits for mainstream
high-performance or low-power applications .Partially depleted (PD) SOIwas the
first SOI technology introduced for high-performance microprocessor applications.
The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures
promise to be the potential "future" technology/device choices. In these
device structures, the short-channel effect is controlled by geometry, and the
thin Si film limits the off-state leakage. For effective suppression of the off-state
leakage, the thickness of the Si film must be less than one quarter of the channel
length. The desired VT is achieved by manipulating the gate work function, such
as the use of midgap material or poly-SiGe. Concurrently, material enhancements,
such as the use of a) high-k gate material and b) strained Si channel for mobility
and current drive improvement, have been actively pursued. As scaling approaches
multiple physical limits and as new device structures and materials are introduced,
unique and new circuit design issues continue to be presented. In this article,
we review the design challenges of these emerging technologies with particular
emphasis on the implications and impacts of individual device scaling elements
and unique device structures on the circuit design. We focus on the planar device
structures, from continuous scaling of PD SOI to FD SOI, and new materials such
as strained-Si channel and high-k gate dielectric.
Depleted [PD] SOI
The PD floating-body MOSFET was the first SOI transistor
generically adopted for high-performance applications, primarily due to device
and processing similarities to bulk CMOS device.
The PD SOI device is largely
identical to the bulk device, except for the addition of a buried oxide ("BOX")
layer. The active Si film thickness is larger than the channel depletion width,
thus leaving a quasi-neutral "floating" body region underneath the channel.
The V T of the device is completely decoupled from the Si film thickness, and
the doping profiles can be tailored for any desired VT. The device offers several
advantages for performance/ power improvement:
Reduced junction capacitance,
Lower average threshold due to positive V BS during switching.
Dynamic loading effects, in which the load device tends to be in high VT state
during switching The performance comes at the cost of some design complexity resulting
from the floating body of the device, such as
Parasitic bipolar effect and
Hysteretic VT variation.
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