This gives an overview of the BlueGene/L Supercomputer. This is a jointly funded
research partnership between IBM and the Lawrence Livermore National Laboratory
as part of the United States Department of Energy ASCI Advanced Architecture Research
Program. Application performance and scaling studies have recently been initiated
with partners at a number of academic and government institutions, including the
San Diego Supercomputer Center and the California Institute of Technology. This
massively parallel system of 65,536 nodes is based on a new architecture that
exploits system-on-a-chip technology to deliver target peak processing power of
360 teraFLOPS (trillion floating-point operations per second). The machine is
scheduled to be operational in the 2004-2005 time frame, at price/performance
and power consumption/performance targets unobtainable with conventional architectures.
IBM has has previously announced a multi-year initiative to build a petaflop scale machine
for calculations in the area of life sciences. The BlueGene/L machine is a first
step in this program, and is based on a different and more generalized architecture
than IBM described in its announcement of the BlueGene program in December of
1999. In particular BlueGene/L is based on an embedded PowerPC processor supporting
a large memory space, with standard compilers and message passing environment,
albeit with significant additions and modifications to the standard PowerPC system.
Significant progress has been made in recent years mapping numerous compute-intensive
applications, many of them grand challenges, to parallel architectures. This has
been done to great success largely out of necessity, as it has become clear that
currently the only way to achieve teraFLOPS-scale computing is to garner the multiplicative
benefits offered by a massively parallel machine.
scale to the next level of parallelism, in which tens of thousands of processors
are utilized, the traditional approach of clustering large, fast SMPs will be
increasingly limited by power consumption and footprint constraints. For example,
to house supercomputers in the 2004 time frame, both the Los Alamos National Laboratory
and the Lawrence Livermore National Laboratory have begun constructing buildings
with approximately 10x more power and cooling capacity and 2-4x more floor space
than existing facilities. In addition, due to the growing gap between the processor
cycle times and memory access times, the fastest available processors will typically
deliver a continuously decreasing fraction of their peak performance, despite
ever more sophisticated memory hierarchies.
approach taken in BlueGene/L (BG/L) is substantially different. The system is
built out of a very large number of nodes, each of which has a relatively modest
clock rate. Those nodes present both low power consumption and low cost. The design
point of BG/L utilizes IBM PowerPC embedded CMOS processors, embedded DRAM, and
system-on-a-chip techniques that allow for integration of all system functions
including compute processor, communications processor,
3 cache levels, and multiple
high speed interconnection networks with sophisticated routing onto a single ASIC.
Because of a relatively modest processor cycle time, the memory is close, in terms
of cycles, to the processor. This is also advantageous for power consumption,
and enables construction of denser packages in which 1024 compute nodes can be
placed within a single rack. Integration of the inter-node communications network
functions onto the same ASIC as the processors reduces cost, since the need for
a separate, high-speed switch is eliminated.
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