During the last two decades, there has been an exponential growth in the
operational speed of microprocessors. Also RAM capacities have been improving
at more than fifty percent per year. However the speed and access time of the
memory have been improving at slower rate. In order to keep up in performance
and reliability with processor technology it is necessary to make considerable
improvements in the memory access time.
Rambus founders emerged with a memory technology-RD RAM. RDRAM memory provides
the highest bandwidth -2.1GB/sec. per pin- from the fewest pins at five-times
the speed of industry available DRAM. The RDRAM memory channel achieves its high-speed
operation through several innovative techniques including separate control and
address buses, highly efficient protocol, low voltage signaling, and precise clocking
to minimize skew between clock and data lines. A single RDRAM device is capable
of transferring data at 1066Mb/sec. per-pin to Rambus-compatible ICs. Data rate
per-pin will increase beyond 1066Mb/sec per pin in the future.
This technology is based on a very high-speed, chip-to-chip interface and has been incorporated into DRAM architectures called Rambus DRAM or RDRAM. It can also be used with conventional processors and controllers to achieve a performance rate that is 100 times faster than conventional DRAMs. At the heart of the Rambus Channel Memory architecture, is ordinary DRAM cells to store information. But the access to those cells, and the physical, electrical and logical construction of a Rambus memory system is entirely new and much, much faster than conventional DRAMs. The Rambus channel transfers data on each edge of a 400 MHz differential clock to achieve an 800- MB/s data rate. It uses a very small number of very high speed signals to carry all the address, data and control information, greatly reducing the pin count and hence cost while maintaining high performance levels. The data and control lines have 800-mV logic levels that operate in a strictly controlled impedance environment and meet the specific high-speed timing requirements. This memory performance satisfies the requirements of the next generation of processors in PCs, servers, workstations as well as communications and consumer applications.
Currently, there are three major groups of memory technology widely available in the market: Synchronous DRAM (SDRAM), Double Data Rate Synchronous DRAM (DDR SDRAM) and RDRAM memory. SDRAM and DDR SDRAM share many architectural and signaling features. Both use a parallel data bus, mainly available in component widths of x8 or x16, both have a single addressing command bus that must be shared to transmit row and column addresses.
DDR SDRAM increases data bandwidth over conventional SDRAM by transmitting data on both edges of the synchronous clock signal using SSTL-2 signaling, thus in theory "doubling" the data rate of the memory. It, However does not double the address command bandwidth of the system by using both the edges of the clock on the command bus, a factor that ultimately limits the performance from using DDR signaling on the data bus.
RDRAM memory takes a totally different approach. It combines a conventional DRAM core with a high-speed serial interface called the RDRAM channel. The Channel uses 16 pins ( 2 bytes) for a data path operating at an effective data rate of 800 MHz per pin by transmitting data on both edges of the clock. To facilitate maximum performance, the RDRAM channel utilizes double data rate signaling on non-multiplexed row and column address command buses.
Since each RDRAM device's data path is as wide as the Channel, a single device can service an entire memory request, unlike SDRAM, which uses multiple devices in parallel to satisfy a request. Up to 32 RDRAM devices can be placed on each Channel without a buffer. The Channel is common to all devices and incorporates the command bus, data bus and a serial control bus for initialization. The RDRAM Channel is uniformly loaded as new devices are added. The RDRAM protocol supports many features that optimize the bandwidth and efficiency of the overall system
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