reconfigurable processor is a microprocessor with erasable hardware that can rewire
itself dynamically. This allows the chip to adapt effectively to the programming
tasks demanded by the particular software they are interfacing with at any given
time. Ideally, the reconfigurable processor can transform itself from a video
chip to a central processing unit (CPU) to a graphics chip, for example, all optimized
to allow applications to run at the highest possible speed.
These chips are like providing a "chip on demand." In practical terms,
this ability can translate to immense flexibility in terms of device functions.
For example, a single device could serve as both a camera and a tape recorder
(among numerous other possibilities): you would simply download the desired software
and the processor would reconfigure itself to optimize performance for that function.
According to a recent Red Herring magazine article, that type of device versatility
may be available by 2003. Reconfigurable processor chip usually contains several
parallel processing computational units known as functional blocks. These functional
blocks are connected in all the possible way. While reconfiguring the chip, the
connections inside the functional blocks and the connections in between the functional
blocks are changing.
That means when a particular software is loaded the present hardware design is
erased and a new hardware design is generated by making a particular number of
connections active while making others idle. This will define the optimum hardware
configuration for that particular software. The key to the design is the small
size of each processing element. The smallest segments of the chip can be defined
with just 50 bits of software code, so the entire chip can be reprogrammed with
just 50,000 bits of software description. It takes just 20 microseconds to reconfigure
the entire processing array.
Reconfigurable processors are currently available from Chameleon Systems, Billions
of Operations (BOPS), and PACT (Parallel Array Computing Technology). Among those
only Chameleon is providing a design environment, which allows customers to convert
their algorithms to hardware configuration by themselvesTECHNOLOGIES
USED IN CHIP
eConfigurable Technology is
used for instantaneous reconfiguration. This technology reconfigures fabric in
one clock cycle and increases voice/data/video channels per chip. As mentioned
earlier, each Slice can be configured independently.
Loading the Background
Plane from external memory requires just 3 µsec per Slice; this operation
does not interfere with active processing on the Fabric.
Background Plane into the Active Plane requires just one clock cycle. with eConfigurable
Technology; the four algorithms are loaded into the entire reconfigurable processing
Fabric one at a time.
C~SIDE Development Tools
Without the necessary software tools, no one but the inventors has been able to
port software to the processors. As a result customers had to give their algorithms
With this software, Chameleon Systems are providing the
ability for the customers to do the programming themselves thus keeping the secrecy
of their algorithms.
The Chameleon Systems Integrated Development Environment (C~SIDE) is a complete
toolkit for designing, debugging and verifying RCP designs. C~Side uses a combined
C language and Verilog (Verilog HDL is a hardware description language used to
design and document electronic systems) flow to map algorithms into the chip's
reconfigurable processing fabric (RPF).
C~SIDE includes an optimized
GNU C compiler for the ARC Processor and an optimized Verilog To Bits (V2B) synthesizer
for the Reconfigurable Processing Fabric., an interactive floor planner, an instruction-set
simulator and a unified debug environment for the ARC core and the RPF.
eBIOS provides a interface between the Embedded Processor
System and the Fabric. eBIOS provides resource allocation, configuration management
and DMA services. The eBIOS calls are automatically generated at compile time,
but can be edited for precise control of any function.
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