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IEEE Seminar Topics

3D ICs Seminar with Free Download


Published on Mar 28, 2016

Abstract

Slide 1 :

WELCOME TO THE SEMINAR

ON

3D ICs

Slide 2 :

Introduction

==> 3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip ( SoC ).

==> The multi-layer chip industry opens up a whole new world of design.

==> With the Introduction of 3-D ICs, the world of chips may never look the same again

==> In the 3-Ddesign architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.

Slide 3 :

Motivation for 3-D ICs

==> Interconnect limited VLSI performance

==> Physical limitations of cu interconnects

==> System – on – a – chip design

Slide 4 :

3D Architecture

--> Figure

Slide 5 :

Advantages of 3D architecture

==>Small size, weight and cost.

==>High reliability.

==>Low power consumption

==>Improved performance

==>Fast operation

Slide 6 :

Limitations

==> Functions at fairly low voltage

==> Limited power dissipation

==> Difficult to achieve low noise and high voltage operation

==> Poor high frequency performance

Slide 7 :

Area and performance estimation of 3D ICs

==> Rent’s Rule
T=kNP -------------(i)

==> 2-D and 3-D Wire-length distributions
I(l)= i(x)dx -----------(ii)

==> Estimating 2-D and 3-D chip area
Arequired = √Ac (PlocLtotal_loc+PsemiLtotal_semi+PglobLtotal_glob)/N

Slide 8 :

Silicon Epitaxial Growth

==> Figure

Slide 9 :

Conclusion

==> The 3 D memory will just the first of a new generation of dense, inexpensive chips that promise to make digital recording media both cheap and convenient enough to replace the photographic film and audio tape.

==> We can understand that 3-D ICs are an attractive chip architecture, that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip.

==> The multilayer chip building technology opens up a whole new world of design like a city skyline transformed by skyscrapers

Slide 10 :

References

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