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Definition
VHDL (VHSIC Hardware Description Language) is a language for describing hardware.
Its requirement emerged during the VHSIC development program of the US Department
of Defense. The department organized a work shop in 1981 to lay down the specifications
of a language which could describe hardware at various levels of abstractions,
could generate test signals and record responses, and could act as a medium of
information exchange between the chip foundries and the CAD tool operators. However,
due to military restrictions, it remained classified till 1985. Structural
Descriptions
1.Building
Blocks
To make designs more understandable and maintainable, a design
is typically decomposed into several blocks. These blocks are then connected together
to form a complete design. Using the schematic capture approach to design, this
might be done with a block diagram editor. Every portion of a VHDL design is considered
a block. A VHDL design may be completely described in a single block, or it may
be decomposed in several blocks. Each block in VHDL is analogous to an off-the-shelf
part and is called an entity. The entity describes the interface to that block
and a separate part associated with the entity describes how that block operates.
The interface description is like a pin description in a data book, specifying
the inputs and outputs to the block. The description of the operation of the part
is like a schematic for the block.
2.Connecting
Blocks
Once we have defined the basic building blocks of our design using
entities and their associated architectures, we can combine them together to form
other designs. This section describes how to combine these blocks together in
a structural description.
3.Data Flow Descriptions
The
VHDL standard not only describes how designs are specified, but also how they
should be interpreted. This is the purpose of having standards, so that we can
all agree on the meaning of a design. It is important to understand how a VHDL
simulator interprets a design because that dictates what the "correct"
interpretation is according to the standard (Hopefully, simulators are not all
100% correct).
The scheme used to model
a VHDL design is called discrete event time simulation. When the value of a signal
changes, we say an event has occurred on that signal. If data flows from signal
A to signal B, and an event has occurred on signal A (i.e. A's value changes),
then we need to determine the possibly new value of B. This is the foundation
of the discrete event time simulation. The values of signals are only updated
when certain events occur and events occur at discrete instances of time.
Since one event causes another, simulation
proceeds in rounds. The simulator maintains a list of events that need to be processed.
In each round, all events in a list are processed, any new events that are produced
are placed in a separate list (and are said to be scheduled) for processing in
a later round. Each signal assignment is evaluated once, when simulation begins
to determine the initial value of each signal.
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