Seminar Topics

IEEE Seminar Topics

Itanium Processor

Published on Aug 15, 2016


The Itanium brand extends Intel's reach into the highest level of computing enabling powerful servers and high- performance workstations to address the increasing demands that the internet economy places on e-business. The Itanium architecture is a unique combination of innovative features, such as explicit parallelism, predication, speculation and much more.

In addition to providing much more memory that today's 32-bit designs, the 64-bit architecture changes the way the processor hardware interacts with code. The Itanium is geared toward increasingly power-hungry applications like e-commerce security, computer-aided design and scientific modeling.

Intel said the Itanium provides a 12-fold performance improvement over today's 32-bit designs. Its "Explicitly Parallel Instruction Computing"(EPIC) technology enables it to handle parallel processing differently than previous architectures, most of which were designed 10 to 20 years ago. The technology reduces hardware complexity to better enable processor speed upgrades. Itanium processors contain "massive chip execution resources", that allow "breakthrough capabilities in processing terabytes of data". Itanium is the first processor to use EPIC(Explicit Parallel Instruction Computing) architecture.Its performance is to be better than the present day Reduced Instruction Set Computing and Complex Instruction Set Computing(RISC & CISC).

In modern Processors,including Itanium,a multiplicity of arithmetic-logic or floating-point on-chip units execute several instructions in parallel.Ideally,increasing the number of execution units should increas the number of extra instructions per clock cycle proportionally.But conventional processors also needs a lot of extra on-chip circuitry to schedule and track the instruction progress,which takes up valuable space,consumes power and add steps to the execution process.

As a result only a slight improvement in the number of instructions per clock cycle occurs when the number of execution units are increased.Instead EPIC architects use a compiler to schedule instructions.

An excellent scheduler ,it makes parallelism explicit to th processor.It bundles instructions into 128-bit packets containing up to three instructions plus information about the interdependencies.Less scheduling and tracking circuitry is needed on the chip and the extra information in each bundle allows the architecture to be scalable so that programs compiled for todays itanium systems will not need recompilation for future generations of the chip


The itanium processor family came about for several reasons,but the primary one was that the processor architecture advances of RISC were no longer growing at the rate seen in the 1980's or the 1990's.Yet,customers continued to demand greater application performance,due to the following developments:

" Increased users and demand(internet)

" Higher bandwidth tasks(streaming)

" Requirements for secure processing(SSL)

" Larger hardware requirements(Very Large Data Bases)

" Support for multi-OS environments(virtual data center,computing as a utility)

The Itanium processor family was developed as a response to address the future performance and growth needs of business,technical ,and scientific users with greater flexibility,better performance and a much greater 'bang for the buck' in the price performance arena.

The Itanium architecture achieves a more difficult goal than a processor that could have been designed with 'price as no object'.Rather,it delivers near-peerless speed at a price that is sustainable by the mainstream corporate market.some of the features that this processor brings to the follow below:

" Floating-point performance for compute intensive applications

" EPIC technology for maximum parallelism &HW\SW synergy

" Scalability from 1-way to128-way+

" 64-bit addressing and high bandwidth