Performance Of Nanoelectronics
Nano electronic devices fall into two classes: tunnel devices and ballistic
transport devices. In Tunnel devices single electron effects occur if the tunnel
resistance is larger than h/e = 25 K §Ù. In Ballistic devices with
cross sectional dimensions in the range of quantum mechanical wavelength of electrons,
the resistance is of order h/e = 25 K §Ù. This high resistance may
seem to restrict the operational speed of nano electronics in general. However
the capacitance values and drain source spacing are typically small which gives
rise to very small RC times and transit times of order of ps or less. Thus the
speed may be very large, up to THz range. The goal of this seminar is to present
the models an performance predictions about the effects that set the speed limit
in carbon nanotube transistors, which form the ideal test bed for understanding
the high frequency properties of Nano electronics because they may behave as ideal
ballistic 1d transistors.
Transport- An Outline
When carriers travel through a semiconductor material,
they are likely to be scattered by any number of possible sources, including acoustic
and optical phonons, ionized impurities, defects, interfaces, and other carriers.
If, however, the distance traveled by the carrier is smaller than the mean free
path, it is likely not to encounter any scattering events; it can, as a result,
move ballistically through the channel. To the first order, the existence of ballistic
transport in a MOSFET depends on the value of the characteristic scattering length
(i.e. mean free path) in relation to channel length of the transistor.
scattering length, l , can be estimated from the measured carrier mobility where
t is the average scattering time, m* is the carrier effective mass, and vth is
the thermal velocity. Because scattering mechanisms determine the extent of ballistic
transport, it is important to understand how these depend upon operating conditions
such as normal electric field and ambient temperature.
On Normal Electric Field
state-of-the-art MOSFET inversion layers, carrier scattering is dominated by phonons,
impurities (Coulomb interaction), and surface roughness scattering at the Si-SiO2
interface. The relative importance of each scattering mechanism is dependent on
the effective electric field component normal to the conduction channel. At low
fields, impurity scattering dominates due to strong Coulombic interactions between
the carriers and the impurity centers. As the electric field is increased, acoustic
phonons begin to dominate the scattering process. At very high fields, carriers
are pulled closer to the Si-SiO2 gate oxide interface; thus, surface roughness
scattering degrades carrier mobility. A universal mobility model has been developed
to relate field strength with the effective carrier mobility due to phonon and
surface roughness scattering:
When the temperature is changed, the relative importance
of each of the aforementioned scattering mechanisms is altered. Phonon scattering
becomes less important at very low temperatures. Impurity scattering, on the other
hand, becomes more significant because carriers are moving slower (thermal velocity
is decreased) and thus have more time to interact with impurity centers. Surface
roughness scattering remains the same because it does not depend on temperature.
At liquid nitrogen temperatures (77K) and an effective electric field of 1MV/cm,
the electron and hole mobilities are ~700 cm2/Vsec and ~100 cm2/Vsec, respectively.
Using the above equations, the scattering lengths are approximately 17nm and 3.6nm.These
scattering lengths can be assumed to be worst-case scenarios, as large operating
voltages (1V) and aggressively scaled gate oxides (10Å) are assumed. Thus,
actual scattering lengths will likely be larger than the calculated values.
device design considerations in maximizing this scattering length will be discussed
in the last section of this paper. Still, the values calculated above are certainly
in the range of transistor gate lengths currently being studied in advanced MOSFET
research (<50nm). Ballistic carrier transport should thus become increasingly
important as transistor channel lengths are further reduced in size. In addition,
it should be noted that the mean free path of holes is generally smaller than
that of electrons. Thus, it should be expected that ballistic transport in PMOS
transistors is more difficult to achieve, since current conduction occurs through
hole transport. Calculation of the mean scattering length, however, can only be
regarded as a first-order estimation of ballistic transport.
accurately determine the extent of ballistic transport evident in a particular
transistor structure, Monte Carlo simulation methods must be employed. Only by
modeling the random trajectory of each carrier traveling through the channel can
we truly assess the extent of ballistic transport in a MOSFET.
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