In this page, you can find VLSI Thesis Topics or Ideas , VLSI Projects and IEEE Based MATLAB Projects for the Final Year Engineering or Graduate Students. Also Explore VHDL Projects, Abstracts, Synopsis in PPT, PDF or DOC Format for ECE and EEE Students, MSc or BSc Graduates.  

VLSI Thesis Topics or Ideas


4 BIT SFQ Multiplier

We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. .....>>>>Read More


Lossless Implementation Of Daubechies 8-Tap Wavelet Transform

A new mapping scheme and its hardware implementation to error-freely compute the Daubechies 8-tap wavelet transform is presented. The multidimensional technique maps the irrational transform basis coefficients with integers and results in considerable reduction in hardware and power consumption. When implemented in Xilinx FPGA, the scheme costs 518 logic cells, 186 registers and runs at a frequency of 71MHz......>>>>Read More


High-Accuracy Fixed-Width Modified Booth Multipliers

The fixed-width multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. This paper presents the design of high-accuracy fixed-width modified Booth multipliers. To reduce the truncation error, we first slightly modify the partial product matrix of Booth multiplication and then derive an effective error compensation function that makes the error distribution be .....>>>>Read More


High-Speed Low-Power Viterbi Decoder Design For TCM Decoders

High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. We propose a pre-computation architecture incorporated with $T$-algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much......>>>>Read More


8 Bit PICCO Processor

The picoProcessor (pP) is an 8-bit processor. The picoProcessor has separate instruction and data memories. The instruction memory is 4K instructions in size, and data memory is 256 bytes. The picoProcessor can also address I/O devices using up to 256 input ports and 256 output ports. Within the processor there are eight 8-bit general purpose registers r0 to r7. r0 is always read as zero and ignores writes. There is also a return address stack of depth 4, an interrupt return register and Zero(Z) and Carry(C) condition codes......>>>>Read More


A Framework for Correction of Multi-Bit Soft Errors

With the continuous decrease in the minimum feature size and increase in the chip density due to technology scaling, on-chip L2 caches are becoming increasingly susceptible to multi-bit soft errors. The increase in multi-bit errors could lead to higher risk of data corruption and potentially result in the crashing of application programs. Traditionally, the L2 caches have been protected from soft errors using techniques such as: 1) error detection/correction codes; 2) physical interleaving of cache bit lines to convert multi-bit errors into single-bit errors;.....>>>>Read More



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