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Abstract

The main aim in this project is to design a combination lock state machine design using VHDL programming. In this design we follow some procedure to execute the program like compilation, stimulation and execution of the waveform, which results the combinational lock machine it is also an example of a mealy machine.

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In VHDL system the hardware description language is used to describe the digital systems were it is used in integrated circuits or on printed circuits boards. One of the main advantages of the VHDL is that it allows the system to be modified and verified before the original design is translated into a real one.

In general I have explained with the introduction about VHDL programming and state graphs with truth table of the combinational lock machine.

Then the general structure of the VHDL Program and design styles in which includes Behavioural style, structural flow and data flow of this system. In other hand in order to develop this system programming, we are using system software called MODELSIM. It as ability to compilation, stimulation and execution of the waveform

LANGUAGE USED:

VHDL

TOOLS REQUIRED:

Simulation: ModelSim XE III 6.4b.

Synthesis: XiLinx ISE 10.1.