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Abstract

A logic design style known as phase difference-based logic (PDBL) has several benefits with respect to security and testing. An existing design method for PDBL circuits has so far been lacking an important component, a register.

In this paper, we present the design of a speed independent PDBL register and a timed PDBL register, which can be used in asynchronous or synchronous circuits. Comparisons are presented in terms of speed, size, and power consumption

Register For Phase Difference Based Logic

 

PROPOSED SYSTEM:

In the proposed system, two types of register are used speed independent PDBL register and Timed PDBL register and comparison are made

LANGUAGE USED:

VHDL

TOOLS REQUIRED:

Simulation: ModelSim XE III 6.4b.

Synthesis: XiLinx ISE 10.1.