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Novel Area-Efficient FPGA Architectures

Abstract

This paper presents four novel area-efficient field-programmable gate-array (FPGA) bit-parallel architectures of finite impulse response (FIR) filters that smartly support the technique of symmetric signal extension while processing finite length signals at their boundaries. The key to this is a clever use of variable-depth shift registers which are efficiently implemented in Xilinx FPGAs in the form of shift register logic (SRL) omponents. Comparisons with the conventional architecture of FIR filter with symmetric boundary processing showconsiderable area saving especially with long-tap filters.

For instance, our architecture implementation of the 8-tap low Daubechies-8 FIR filter achieves 30% reduction in the area requirement (in terms of slices) compared to the conventional architecture while maintaining the same throughput. Two of the above-cited novel architectures are dedicated to the special case of symmetric FIR filters. The first architecture is highly area-efficient but requires a clock frequency doubler. While this reduces the overall processing speed (to a maximum of 2), it does maintain a high throughput. Moreover, this speed penalty is cancelled in bi-phase filters which are widely used in multirate architectures (e.g., wavelets).

Our second symmetric FIR filter architecture saves less logic than the first architecture (e.g., 10% with the 9-tap low Biorthogonal 9&7 symmetric filter instead of 37% with the first architecture) but overcomes its speed penalty as it matches the throughput of the conventional architecture

LANGUAGE USED:

VHDL

TOOLS REQUIRED:

  • Simulation: modelsim5.8c
  • Synthesis: Xilinx 9.1

 

 

 

 

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