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The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system.

This load is reduced by supplementing the main processor with Co- Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc.

The speed of ALU depends greatly on the multiplier Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc.

The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications.

Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications [2].

One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications [2, 3] .

This work presents different multiplier architectures. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier




Simulation: modelsim5.8c

Synthesis: Xilinx 9.1