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A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. The only linear function of single bits is xor, thus it is a shift register whose input bit is driven by the exclusive-or (xor) of some bits of the overall shift register value.

The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle

Linear Feedback Shift Register (LFSR) structures are widely used in digital signal processing and communication systems, such as BCH, CRC. Many current functions such as Scrambling, Convolutional Coding, CRC and even Cordic or Fast Fourier Transform can be derived as Linear Feedback Shift Registers (LFSR) In high-rate digital systems such as optical communication system, throughput of 1Gbps is usually desired.

The serial input/output operation property of LFSR structure is a bottleneck in such systems and parallel LFSR architecture is thus required.

This work presents a three-step high-speed VLSI architecture for LFSR structures, this paper proposes improved three-step LFSR architecture with both higher hardware efficiency and speed. This architecture can be applied to any LFSR structure for high-speed parallel implementation


• Reduced Power dissipation

• Higher throughput rate.

• Higher processing speed

• Fast Computation .

• LFSR can rapidly transmit a sequence that indicates high-precision relative time offsets


• Pattern Generators

• Built-In Self-Test(BIST)

• Encryption.

• LFSR can be used for generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences.

Pseudo-Random Bit Sequences




Simulation: modelsim5.8c

Synthesis: Xilinx 9.1