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Abstract

Protocols are commonly used today to connect IP blocks on structured SoCs . Generally Protocol is the back-bone of the SoC and its failure usually leads to a non-functional chip.

In present market, various types of standard protocols are available and are used in SoC which requires a bridge to pass the information from one type of protocol to other type of protocol safely and without any data loss.

Basic idea is to provide a bus bridge between the two protocols in order to perform the proper and lossless communication between the IP cores which using various protocols on the System on Chip (SOC) system.

Basically, an SOC is a system which is considered as a set of components and interconnects among them. The dataflow will happen in the system in order to achieve a successful process and hence for which the various interfaces is required. If these interfaces have issues, then the process to be achieved will fail which leads to fail of whole application.

This project is chosen because currently the issues are increased in the industries due to the lack of proper data transferring between the IP cores on the System on Chip (SOC) system. Open Core Protocol (OCP) and AMBA - Advanced High Performance Bus (AHB) protocol are standard and commonly used protocols.

In this work, the bus bridge was designed to interface these protocols which plays a vital role in SoC application such as it may lead to application failure, if it doesn't work properly . Initially OCP and AHB protocols will be modeled separately using VHDL and are simulated. Basically Bus Bridge should convey the command and data of AHB formats to acceptable OCP formats.

This conversion does not ensure proper communication unless the timings of each protocol were met. Hence the interconnecting Bus Bridge wrapper between Core Centric Protocol (OCP) and Bus Centric Protocol (AHB) should be designed with proper timing delay

APPLICATION:

• Since it is an IP block, it can be used in any kind of SOC Application. This can be used between any IP cores

ADVANTAGES:

This bus bridge will provide lossless communication between two IP Cores

The main advantage of this OCP Protocol used in this is that it can be configured with respect to the application which reduces the area and design time

LANGUAGE USED:

VHDL

TOOLS REQUIRED:

Simulation: modelsim5.8c

Synthesis: Xilinx 9.1