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Double Data Rate (DDR) SDRAMs have been prevalent in the PC memory market in recent years and are widely used for networking systems. These memory devices are rapidly developing, with high density, high memory bandwidth and low device cost.

However, because of the high-speed interface technology and complex instruction-based memory access control, a specific purpose memory controller is necessary for optimizing the memory access trade off.

In this paper, a specific purpose DDR3 controller for high-performance table lookup is proposed and a corresponding lookup circuit based on the Hash-CAM approach is presented.

Content Addressable Memory (CAM) based techniques are widely used in network equipment for fast table look up.

However, in comparison to Random Access Memory (RAM) technology, CAM technology is restricted in terms of memory density, hardware cost and power dissipation. CAM based lookup circuit's technology having better performance, higher memory density and lower cost.

In this paper, an advanced DDR3 memory controller architecture for high-performance table lookup is designed with a high performance Hash-CAM based lockup circuit and its functionality is verified




Simulation: modelsim5.8c

Synthesis: Xilinx 9.1